--test14.e\
--generate random sequence to S0 after that to S1

<'

import ../examples/vv_ahblite_config;
import ../e/vv_ahblite_master_seq_lib;

extend M0 MAIN vv_ahblite_master_sequence {
    
	!incr4 : INCR4_RW vv_ahblite_master_sequence;
	!incr8 : INCR8_RW vv_ahblite_master_sequence;
	!incr16 : INCR16_RW vv_ahblite_master_sequence;
	
	!wrap4 : WRAP4_RW vv_ahblite_master_sequence;
	!wrap8 : WRAP8_RW vv_ahblite_master_sequence;
	!wrap16 : WRAP16_RW vv_ahblite_master_sequence;
	
	!incr : INCR_RW vv_ahblite_master_sequence;
		
	!wrseq : SINGLE_WRITE vv_ahblite_master_sequence;
    !rdseq : SINGLE_READ vv_ahblite_master_sequence;
	        
    num : uint;
    keep num in [50..100];
           
    body() @driver.clock is only {
    	
    	var addr: uint (bits:32); 
    	var busy: uint;
    	var write: bit;
    	var hit : uint;
        	
    	for i from 1 to num do {
    		
    		gen hit keeping {it in [1..9];};
    		
    		if ( i%2 == 0 ) {gen addr keeping {it in [0..32767];}; }
    		else {gen addr keeping {it in [32768..65535];}; };
    		
    		gen busy keeping {it in [0..6];};
    		gen write;
    		
    		case hit{
        	1:  { do incr4 keeping
        		{
            	.start_address == addr;
            	.busy == busy;
            	.write == write;
            	}; 
        	};
        	2:  { do incr8 keeping
        		{
            	.start_address == addr;
            	.busy == busy;
            	.write == write;
            	}; 
        	};
        	3:  { do incr16 keeping
        		{
            	.start_address == addr;
            	.busy == busy;
            	.write == write;
            	}; 
        	 };
        	4:  { do wrap4 keeping
        		{
            	.start_address == addr;
            	.busy == busy;
            	.write == write;
            	}; 
        	 };
        	5:  { do wrap8 keeping
        		{
            	.start_address == addr;
            	.busy == busy;
            	.write == write;
            	}; 
        	 };
        	6:  { do wrap16 keeping
        		{
            	.start_address == addr;
            	.busy == busy;
            	.write == write;
            	}; 
        	 };
        	7:  { do incr keeping
        		{
            	.start_address == addr;
            	.busy == busy;
            	.write == write;
            	}; 
        	 };
        	8:  { do wrseq keeping
        		{
            	.start_address == addr;
            	.idle == busy;
            	}; 
        	 };
        	9:  { do rdseq keeping
        		{
            	.start_address == addr;
            	.idle == busy;
            	}; 
        	 };
        	default: {message (LOW, "skipped DO, because gen num = ", hit);};
        	};
    		       
    	};
    }; 

}; 

extend MAIN vv_ahblite_slave_sequence {

    -- The slave sequence driver is a reactive sequence driver.
    -- This sets its default to never runs out of sequence items.
    keep soft count == MAX_UINT;
    
    body() @driver.clock is only {
    	for i from 1 to count {
    		do response keeping {
    	soft	.wait_states_num == select {
			    	80: 0;
			    	5: 1;
			    	5: 2;
			    	10: [4..16];
		 };
    			
//    	soft .ready == select {
//	    	10: 0; --30% cases add wait states
//	    	90: 1; --70% no wait state
//	    };
	    
	    soft .response == select {
	    	00: 1; -- error response
	    	90: 0; -- OK response
	    };
		   			
    		}; // do term keeping...
    	}; // for i from 1 to...
    }; // body() @driver....
    
};

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